Product Overview

The Keysight P5570A PCIe 6.0 Protocol Analyzer introduces a new form factor which is easily deployable in the lab bench environment to enable deep protocol analysis of a PCIe system with unparallel signal integrity.  Locate protocol errors or validate device operations by viewing data from the physical layer all  through the transactional layer with ease.

• Decode up to 64GT/s with support of x4, x8 and x16
• Utilize up to 16GB of trace memory aided by on-board data compression
• PHY Layer (TS1/TS2/Ordered sets), Link Layer (ACK/NACK, Sequencing Numbers, Replay) Transaction Layer (Memory, Config, I/O read/writes)
• Supports both FLIT and non-FLIT modes with a dedicated Flit Viewer
• Combined Analyzer and Exerciser Software GUI
• Powerful trigger and filter engine
• Stable and solid mechanical connection from device to the system under test

Key Features

Use Case: Analyze Traffic between Root Complex and Endpoint A common use case for the Keysight P5570A PCIe 6.0 Analyzer is to sit between a PCIe 6.0 capable root complex and a PCIe 6.0 endpoint. The analyzer will capture and decode PCIe signals between the root complex and the endpoint while also passing the signals between the devices through without interference. The Keysight P5570A Analyzer uses an independent power supply, and passes power supplied from the Host System on to the Endpoint without interference.

Backplane Test Platform The Keysight P5563B PCIe 6.0 Protocol Backplane Test Platform features SI enhancements to reduce crosstalk and improve signal integrity, where low-loss material in utilized to support reliable connections at 64GT/s. CEM form factor for endpoint devices.   Integrated low noise power supply with Auxiliary PCIe power available for high power endpoint devices  Stable mechanical construction for reliable operation during bring-up  One pair of CEM slots for connecting the Exerciser with a DUT

Powerful Triggering and Filtering

The most difficult bugs to solve are intermittent with no obvious cause. Finding the root of these troublesome issues often involves setting up for long capture times. But capturing lots of data is not helpful if it cannot effectively be analyzed. Scrolling through trace captures looking for specific issues that are obscured by retraining events and other protocol ‘storms’ is an ineffective use of time. 
Advanced users depend on finely tuned triggering and filtering settings to capture the traffic that they are most interested in. They avoid massive capture windows that scoop up unwanted data which slows down the analysis process both in porting the data to a PC for viewing as well as needlessly obscuring critical protocol events. The Keysight P5570A PCIe 6.0 Protocol Analyzer was designed with this use case in mind. As such, it provides both Simple and Advanced triggering modes.

• Simple triggers are provided that are quick for users to apply and customize.
• Advanced Triggers can be configured to apply a chain of If/Then logic steps to the trigger. In this way specific protocol events can be captured easily, even if they occur only after a complex series of previous events that may span a long time period.  

To extend this capability even further filtering can be applied to ignore certain traffic events to extend the capture window without clogging up the capture log with unneeded data. 

Traffic Decode and Analysis Capability

Solving protocol issues involves a variety of skill sets and debugging tools. Some issues require being able to see specific fields in a packet. Other problems require having an overall view of traffic patterns and errors in a given time frame. To support these needs the Keysight P5570A PCIe 6.0 Protocol Analyzer software provides several different protocol views to enable engineers to use the tool most suited to the problems they are working on. 

Lane View Lane view provides the user with a view of exactly what data is appearing on which lane of the PCIe link. With a mouse over the user can see what packet types individual bytes are associated with. Thus, in a single simple view, the user is given a comprehensive understanding of the protocol makeup.

LTSSM Overview Proper Link Training is critical to solid PCIe performance, and it is often the source of many issues. Physical differences in channels and products are manifested at the protocol layer via the LTSSM. The LTSSM Overview allows validation engineers to see progression through the LTSSM and a decode of which state both the Upstream and Downstream ports are in at a given moment. The LTSSM Overview is a powerful tool for debugging one of the most difficult and complex aspects of PCIe protocol.

FLIT Viewer View and examine FLITs in the up and downstream traffic through the FLIT Viewer.  The ability to filter through a particular FLIT type eases the task of checking the status for errors or no errors in the FEC and also if CRC passes or otherwise.   Available FLIT type, eg. Payload, Nop, Idle, Fail, Pass, etc.

The P5570A PCIe 6.0 Protocol Analyzer is widely used across the following fields and application scenarios:
1. High-Speed Interface Protocol Debugging and Verification
The analyzer supports PCIe protocols from PCIe 6.0 down to PCIe 1.0, as well as CXL 1.1/2.0, with a maximum decoding speed of up to 64 GT/s. It is ideal for real-time analysis of protocol layers in high-speed data transmission. Examples include:
        •  Servers/Data Centers: Monitors PCIe bus performance, detects link negotiation status (e.g., LTSSM link state machine), signal quality, and data transfer rates, ensuring efficient communication between servers and storage devices.
        •  Communication Equipment: Tests the stability of PCIe interfaces in 5G and IoT applications, optimizing the reliability of high-speed data transmission.

2. Signal Integrity and Equalization Optimization
Thanks to its innovative CEM card design, the analyzer can be directly connected to the system or device under test, minimizing signal attenuation caused by traditional chassis and long cables. Its built-in equalization function improves signal integrity, making it suitable for:

        •  Hardware Development: Debugging PCIe 6.0 physical layer (PHY) characteristics, such as TS1/TS2 ordered set analysis.

3. Multi-Layer Protocol Decoding and Fault Diagnosis
Supports full protocol stack analysis from the physical layer to the transaction layer:
        •  Link Layer: Detects ACK/NACK sequences, replay mechanisms, and sequence number errors.
        •  Transaction Layer: Traces memory read/write operations and configuration requests to identify data transmission bottlenecks or abnormal behavior.
        •  FLIT Mode Support: Conducts dedicated testing on the Flow Control Unit (FLIT), a new feature introduced in PCIe 6.0.

4. Compatibility with Lab and Production Test Environments
Its compact design integrates the analyzer with the interposer, saving space and eliminating complex installation requirements. This makes it suitable for:
        •  R&D Labs: Rapid setup of test platforms supporting x4/x8/x16 lane widths, with up to 16 GB of trace memory for extended data capture.
        •  Production Line Testing: Enables fast verification of large batches of devices through automation scripts (e.g., trigger engine and filtering functions).

5. Cross-Industry Comprehensive Applications
Beyond the above scenarios, the device is also widely used in:
        •  Consumer Electronics: Verifying PCIe compatibility between high-performance graphics cards, solid-state drives (SSDs), and motherboards.
        •  Medical Devices and Industrial Controls: Ensuring high reliability and low-latency communication in critical systems.