Product Overview
Simplified, time-efficient testing is essential when you are developing next-generation computer, consumer, or communication devices. The Keysight M8000 Series is a highly-integrated bit error ratio (BER) test solution for physical layer characterization, validation, and compliance testing. With support for a wide range of data rates and standards, the M8000 Series provides accurate, reliable results that accelerate your insight into the performance margins of high-speed digital devices.
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Pulse amplitude modulation 4 (PAM4) and non-return-to-zero (NRZ) formats software-selectable using one piece of hardware
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NRZ data rates from 2 to 64 Gbit/s pattern generation and error analysis
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PAM4/6/8 data rates from 2 to 120 GBd pattern generation and up to 120 GBd error analysis (when used with a UXR-Series oscilloscope)
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Built-in clock / data recovery and equalization from 2 to 120 Gbaud
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Integrated de-emphasis and adjustable intersymbol interference (ISI)
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Multi-channel capabilities
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Flexible hardware ensures investment protection as your application needs change
Key Features
Receiver Characterization and Compliance Testing
Keysight’s bit error ratio test (BERT) system enables the most accurate physical-layer design verification of high-speed communication and multigigabit digital interfaces. Our expert-level support will help you select the high-performance hardware, control software, receiver test, and automation tools needed to help you master your design.
Whether you are working on data center or computing interface technologies, Keysight BERTs offer the most comprehensive choices, from affordable manufacturing test to high-performance characterization and compliance test.
The Keysight BERT supports symbol rates up to 120 Gbaud with non-return-to-zero and pulse amplitude modulation 4/6/8 coding schemes. It also supports digital interfaces such as PCI Express®, USB, MIPI, Thunderbolt, DisplayPort, SATA / SAS, electrical and optical Ethernet 10G / 100G / 400G / 800G / 1.6T, OIF-CEI, Fibre Channel, and PON.
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Pulse Amplitude Modulation (PAM)
The 400 Gigabit Ethernet (GE) standards define four-level PAM (PAM4) multilevel signaling as a recommended modulation format to implement serial 400GE data center interfaces. This is an evolution from the two-state NRZ modulation used in 100GE. PAM4 effectively doubles the data rate for a link bandwidth at the expense of reduced signal to noise ratio (SNR).
You require new measurements to characterize impairments that were not an issue in previous NRZ designs. We can help you ensure accurate and repeatable results to accelerate the development of your PAM4 interface components and systems.
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M8050A high-performance BERT
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Up to 120G Baud for NRZ and PAM4
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PAM6 and PAM8 encoding for 224 Gbps interfaces
M8040A high-performance BERT
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Up to 64 Gbaud PAM4 and NRZ
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Serve both data center (PAM4) and computing (NRZ) with the same two hardware modules via software upgrades
J-BERT M8020A
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Up to 32 Gbit/s NRZ
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Only capable of NRZ generation and analysis
All modules for the M8040A and M8020A are controlled via the M8070B system software.
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Key specifications
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M8020A
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M8040A
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M8050A
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Symbol rate
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PG: 0.256 to 16 GBd
ED: 2 to 16 GBd
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PG:2 to 64 GBd
ED:2 to 58 GBd
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PG:2 to 120 GBd
ED(UXR):14 to 120 GBd
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Channels per PG module
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1 or 2 (2-slot AXIe module incl. clock)
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1 or 2 (2-slot AXIe module incl. clock)
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1 or 2 (2 or 3 AXIe slots + 1 slot for clock module)
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Line coding
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NRZ
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NRZ、PAM4、PAM3
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NRZ、PAM4、PAM6、PAM8
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Output amplitude
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100 mV to 2.4 Vpp dif
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0.16 to 1.8 Vpp, diff @ 58 GBd
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0.1 to 1.6 Vpp, diff @ 120 GBd
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De-emphasis
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8 taps
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5 taps, 1.6% resolution
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7 taps, 0.5% resolution
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Intrinsic random jitter
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300 fs rms typical
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<10 mUl rms @>52 Gbd
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<300 fs rms
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Transition time (20/80)
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12 ps typical
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9 ps @>32 GBd
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7 ps @64 Gbd
4 ps@120 Gbd
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Jitter injection
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SJ (LF, HF), RJ, BUJ, Clk/2
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SJ (LF, HF), RJ, BUJ, Clk/2
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SJ (LF, HF), RJ, BUJ, Clk/2
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Error analysis & interactive link training
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Up to 16 G Interactive link training for PCIe, USB
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Up to 58 GBd with M8046A Interactive link training for PCIe, USB
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Up to 120 GBd with UXR Up to 58 GBd with M8046ASJ (LF, HF), RJ, BUJ, Clk/2
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Key applications
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PCle 4.0、USB、SATA 6G
SAS 24G、DP、SD-UHS II、TBT
MIPI、DDR5、PON、64G FC
10/40/100 GbE、OIF-CEI-26G
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PCle 5.0、USB4、CCIX、SATA、SAS
PON 64G/128G FC
100/200/400 GbE
OIF-CEI-56G/112G
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800G and 1.6T, others: planned with future release
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The M8000 series bit error rate testers are primarily applied in the physical layer verification and testing of high-speed digital signal designs. With capabilities ranging from basic signal integrity analysis to performance evaluation of complex multi-channel systems, the following outlines its core application scenarios and technical support:
1. Physical Layer Receiver Characterization and Verification
The M8000 series supports the following scenarios through high-precision bit error rate (BER) testing and signal integrity analysis:
• High-Speed Interface Testing:
-- Supports physical layer verification of high-speed bus protocols such as PCIe Gen6 (64 GT/s), USB4, and Thunderbolt. It simulates real channel conditions using built-in jitter injection, equalization (CTLE), and inter-symbol interference (ISI) functions.
-- For PAM4/6/8 modulated signals, it provides up to 120 GBaud error analysis capability, suitable for testing 400G/800G Ethernet and optical modules.
• Data Center Interconnect Validation: Used for BER testing of backplanes, high-speed cables, and optical interconnects in 100G/200G/400G/800G Ethernet (e.g., CEI-112G, InfiniBand HDR), ensuring stable and low-error data transmission.
2. Parallel Testing in Multi-Channel and Complex Scenarios
Its modular design supports multi-channel expansion, addressing crosstalk and synchronization challenges in high-speed systems:
• Multi-Channel Parallel Testing: Through a 14-slot AXIe chassis (such as the M8030A), it enables up to 10-channel synchronized testing. This is ideal for applications like PCIe 16-lane ASICs and multi-channel passive optical networks (PON), avoiding signal loss introduced by traditional RF switches.
• Link Training and Protocol Interaction: Simulates link training (Link Training) of protocols such as PCIe, supporting interactive negotiation to help devices under test quickly enter loopback mode for protocol compatibility validation.
3. Manufacturing Test and Compliance Verification
• Manufacturing Environment Adaptability: Offers a cost-effective manufacturing test solution. Using automation scripts (e.g., N5990A software), it enables fast BER testing of large batches of devices, covering chip-level, transceiver module, and system-level product factory verification.
• Standard Compliance Testing: Supports compliance testing per international standards such as PCI-SIG and USB-IF. Built-in calibration ensures repeatable results, meeting certification requirements for servers, consumer electronics, and more.
4. Chip and Component-Level Testing
• High-Speed Chip Verification: Provides precise clock data recovery (CDR) and de-emphasis functions for components such as SERDES and AOC (Active Optical Cables), evaluating performance margins under complex noise environments.
• Mobile and IoT Device Testing: Supports BER testing on MIPI interfaces, meeting the verification needs of low-power, high-speed interfaces used in smartphones and IoT devices.
5. Future Compatibility and Expandability
• Flexible Upgrades: Based on an AXIe architecture hardware platform, it can be upgraded via software to support emerging standards such as CXL 3.1 and 1.6T Ethernet, protecting user investments.
• Cross-Industry Coverage: From consumer electronics to automotive electronics (e.g., vehicle computing units), its multi-protocol support meets high-speed interconnect testing needs across different industries.